EPM5130QC-1 vs EPM5130WC-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130QC-1 sa pamamagitan ng Altera at EPM5130WC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130QC-1 | EPM5130WC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Product Type | UV-Erasable / OTP Complex PLD (CPLD) | UV-Erasable PLD (CPLD) |
| Logic Cells / Macrocells | 128 macrocells | — |
| Usable Gates (marketing) | 5130 gates | — |
| Speed Grade | -1 | -2 (45 ns) |
| Packhaging | PQFP-100 (windowed ceramic) | — |
| Terminal Pitch | 0.635 mm | 0.650 mm |
| Process Technology | CMOS | CMOS |
| Configuration Memory | UV-Erasable EPROM | UV-erasable CMOS EEPROM cells |
| Volte ng Pagbibigay | 5 V (single) | — |
| Temperature na Operasyon | Commercial (0 C to +70 C) | 0 °C to 70 °C (Commercial) |
| Programmable Polarity | Yes (per macrocell) | — |
| Boundary Scan / JTAG | Per MAX 5000 family | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Propagation Delay (tPD) | — | 45 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Dedicated Inputs | — | 19 |
| User I/O Lines | — | 48 |
| Total Inputs (I/O + dedicated) | — | 68 |
| Package Type | — | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Logic Elements | — | AND/OR array with programmable macrocell register |