EPM5130QC-1 vs EPM5130WC-2 比較
詳細並排比較 EPM5130QC-1 由 Altera 與 EPM5130WC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5130QC-1 | EPM5130WC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Product Type | UV-Erasable / OTP Complex PLD (CPLD) | UV-Erasable PLD (CPLD) |
| Logic Cells / Macrocells | 128 macrocells | — |
| Usable Gates (marketing) | 5130 gates | — |
| Speed Grade | -1 | -2 (45 ns) |
| 封裝 | PQFP-100 (windowed ceramic) | — |
| Terminal Pitch | 0.635 mm | 0.650 mm |
| Process Technology | CMOS | CMOS |
| Configuration Memory | UV-Erasable EPROM | UV-erasable CMOS EEPROM cells |
| 供應電壓 | 5 V (single) | — |
| 工作溫度 | Commercial (0 C to +70 C) | 0 °C to 70 °C (Commercial) |
| Programmable Polarity | Yes (per macrocell) | — |
| Boundary Scan / JTAG | Per MAX 5000 family | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Propagation Delay (tPD) | — | 45 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Dedicated Inputs | — | 19 |
| User I/O Lines | — | 48 |
| Total Inputs (I/O + dedicated) | — | 68 |
| Package Type | — | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Logic Elements | — | AND/OR array with programmable macrocell register |