EPM5130WC-2 vs EPM5130QC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130WC-2 sa pamamagitan ng Altera at EPM5130QC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130WC-2 | EPM5130QC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable PLD (CPLD) | UV-Erasable / OTP Complex PLD (CPLD) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 45 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Temperature na Operasyon | 0 °C to 70 °C (Commercial) | Commercial (0 C to +70 C) |
| Process Technology | CMOS | CMOS |
| Dedicated Inputs | 19 | — |
| User I/O Lines | 48 | — |
| Total Inputs (I/O + dedicated) | 68 | — |
| Package Type | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing | — |
| Terminal Pitch | 0.650 mm | 0.635 mm |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | UV-erasable CMOS EEPROM cells | UV-Erasable EPROM |
| Speed Grade | -2 (45 ns) | -1 |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | AND/OR array with programmable macrocell register | — |
| Family | — | MAX 5000 |
| Logic Cells / Macrocells | — | 128 macrocells |
| Usable Gates (marketing) | — | 5130 gates |
| Packhaging | — | PQFP-100 (windowed ceramic) |
| Volte ng Pagbibigay | — | 5 V (single) |
| Programmable Polarity | — | Yes (per macrocell) |
| Boundary Scan / JTAG | — | Per MAX 5000 family |