EPM5130WM883B-2 vs EPM5130WC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130WM883B-2 sa pamamagitan ng Altera at EPM5130WC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5130WM883B-2 EPM5130WC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 —
Device Type UV PLD (UV-erasable programmable logic device) —
Macrocells 128 —
Logic Array Blocks (LABs) 8 —
Propagation Delay (tPD, -2 grade) 45 ns —
Propagation Delay (tPD, -1 grade) 55 ns (EPM5130WM883B base) —
Dedicated Inputs 19 19
User I/O Pins 48 —
Total Inputs 68 —
Total Outputs 48 —
Interconnect Programmable Interconnect Array (PIA) - 8 LAB channels —
Process Technology CMOS CMOS
External Clock Inputs 1 —
Programming Method UV-erasable (windowed package) —
Development Tool MAX+PLUS II —
Military Processing MIL-STD-883 Class B (883B suffix) —
Temperature na Operasyon [DATA_NEEDED: military temperature range] 0 °C to 70 °C (Commercial)
Packhaging [DATA_NEEDED: exact package code] —
Tindminan RoHS unknown [DATA_NEEDED: RoHS status]
Device Family — MAX 5000
Product Type — UV-Erasable PLD (CPLD)
Macrocell Count — 128
Propagation Delay (tPD) — 45 ns
Supply Voltage (VCC) — 4.75 V to 5.25 V
User I/O Lines — 48
Total Inputs (I/O + dedicated) — 68
Package Type — 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing
Terminal Pitch — 0.650 mm
Uri ng Pagpapasok — Surface Mount
Configuration Memory — UV-erasable CMOS EEPROM cells
Speed Grade — -2 (45 ns)
Lead-Free — [DATA_NEEDED: lead-free status]
Logic Elements — AND/OR array with programmable macrocell register

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita