EPM5192AGC84-20 vs EPM5192AJC84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192AGC84-20 sa pamamagitan ng Altera at EPM5192AJC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 ObsoletePagsanggunian na paghahambing
| Parametro | EPM5192AGC84-20 | EPM5192AJC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| Packhaging | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | 84-pin PLCC J-Lead (WQCCJ, J84) |
| Package Code | WPGA | — |
| Erasure Method | UV-Erasable (with OTP window) | — |
| Process Technology | CMOS | CMOS, UV-erasable EEPROM |
| Operating Temperature Grade | Commercial | Commercial |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | — |
| I/O Standard | 5V CMOS / TTL compatible | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Uri ng Pagpapasok | Through-Hole (Pin Grid Array socket) | Surface Mount (J-Lead) |
| Device Type | — | UV-erasable/OTP Complex PLD (CPLD) |
| Propagation Delay (tpd) | — | 33 ns (speed grade -20) |
| Maksimum na Taktiko ng Oras | — | 66.7 MHz |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V |
| User I/O Lines | — | 64 |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus (legacy) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |