EPM5192AJI84-20 vs EPM5192AJC84-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192AJI84-20 sa pamamagitan ng Altera at EPM5192AJC84-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 ObsoletePagsanggunian na paghahambing
| Parametro | EPM5192AJI84-20 | EPM5192AJC84-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 (EPM5192) | — |
| Logic Cells / Macrocells | 192 macrocells | — |
| Device Type | UV-Erasable / OTP Complex PLD | EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tPD) | 33 ns | — |
| Maximum Frequency (fCNT) | 66.7 MHz | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | 5 V (single supply) |
| Process Technology | CMOS | CMOS EPROM |
| Operating Temperature Grade | Industrial | — |
| Package Code | WQCCJ (JEDEC) | — |
| Package Type | 84-pin J-bend Ceramic Chip Carrier (PLCC-84, JI) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Terminal Form | J-Bend | — |
| Number of Terminals | 84 | — |
| Programmability | UV-erasable window + OTP | — |
| Bilang ng Pin | 84 | — |
| Katayuan ng Lifecycle | Obsolete (legacy Altera MAX 5000) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status of EPM5192AJI84-20] | Non-compliant (contains Pb, ceramic windowed package) |
| Family | — | MAX 5000 |
| Macrocells | — | 192 |
| Propagation Delay (tpd) | — | 15 ns |
| Maximum Clock Frequency (fMAX) | — | 83.3 MHz |
| Technology | — | CMOS, UV-erasable EPROM |
| Packhaging | — | 84-pin PLCC (J84C) windowed ceramic |
| Temperature na Operasyon | — | [DATA_NEEDED: commercial/industrial/military grade] |
| Programming Method | — | UV-erase + EPROM programming (windowed package) |
| Logic Blocks | — | 16 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: user I/O count] |