EPM5192ALC84-15 vs EPM5192AJC84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192ALC84-15 sa pamamagitan ng Altera at EPM5192AJC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 ObsoletePagsanggunian na paghahambing
| Parametro | EPM5192ALC84-15 | EPM5192AJC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 (EPM5192) | — |
| Device Type | CPLD / UV-Erasable / OTP Complex PLD | UV-erasable/OTP Complex PLD (CPLD) |
| Macrocells | 192 | 192 |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Propagation Delay (Industry Variant) | 25 ns (per MicrochipUSA listing) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS (EPROM-based) | CMOS, UV-erasable EEPROM |
| Programmability | UV-erasable window / OTP | — |
| Packhaging | 84-pin PLCC (QCCJ, J-bend ceramic) | 84-pin PLCC J-Lead (WQCCJ, J84) |
| Operating Temperature Grade | Commercial | Commercial |
| Terminal Form | J-BEND | — |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Architecture | Programmable Logic Array + Macrocell Registers + PIA interconnect | — |
| Family | — | MAX 5000 |
| Propagation Delay (tpd) | — | 33 ns (speed grade -20) |
| Maksimum na Taktiko ng Oras | — | 66.7 MHz |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V |
| User I/O Lines | — | 64 |
| Uri ng Pagpapasok | — | Surface Mount (J-Lead) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus (legacy) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |