EPM5192GI-2 vs EPM5192GC-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192GI-2 sa pamamagitan ng Intel at EPM5192GC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192GI-2 | EPM5192GC-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable / OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 30 ns | 12 ns typical (-2 grade) |
| Maksimum na Taktiko ng Oras | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | 5 V nominal |
| Operating Temperature Grade | Industrial | — |
| Packhaging | 84-pin PGA (Pin Grid Array) | — |
| Package Code | PGA | — |
| Package Shape | Square | — |
| Terminal Form | PIN/PEG (through-hole) | — |
| Programming Method | UV-erase window (erasable) / OTP | — |
| Process Technology | CMOS | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) |
| Family | — | MAX 5000 |
| Logic Array Blocks | — | 16 (LABs of 16 macrocells each) |
| Usable I/O Pins | — | [DATA_NEEDED: exact user I/O count for PGA package] |
| Counter Frequency | — | 100 MHz minimum |
| Technology | — | CMOS EPROM |
| Programmable Technology | — | UV-erasable / one-time programmable |
| Programming Toolchain | — | Altera MAX+PLUS II |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Temperature na Operasyon | — | Commercial (0C to +70C) |
| Speed Grade | — | -2 |
| Uri ng Pagpapasok | — | Through-hole (PGA socket) |