EPM5192GI-2 vs EPM5192GC-2 比較
詳細並排比較 EPM5192GI-2 由 Intel 與 EPM5192GC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GI-2 | EPM5192GC-2 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable / OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 30 ns | 12 ns typical (-2 grade) |
| 最大時脈頻率 | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | 5 V nominal |
| Operating Temperature Grade | Industrial | — |
| 封裝 | 84-pin PGA (Pin Grid Array) | — |
| Package Code | PGA | — |
| Package Shape | Square | — |
| Terminal Form | PIN/PEG (through-hole) | — |
| Programming Method | UV-erase window (erasable) / OTP | — |
| Process Technology | CMOS | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) |
| Family | — | MAX 5000 |
| Logic Array Blocks | — | 16 (LABs of 16 macrocells each) |
| Usable I/O Pins | — | [DATA_NEEDED: exact user I/O count for PGA package] |
| Counter Frequency | — | 100 MHz minimum |
| Technology | — | CMOS EPROM |
| Programmable Technology | — | UV-erasable / one-time programmable |
| Programming Toolchain | — | Altera MAX+PLUS II |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| 工作溫度 | — | Commercial (0C to +70C) |
| Speed Grade | — | -2 |
| 安裝類型 | — | Through-hole (PGA socket) |