EPM5192GM vs EPM5192GM883B-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192GM sa pamamagitan ng Altera at EPM5192GM883B-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192GM EPM5192GM883B-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Product Family MAX 5000 —
Device Type UV Erasable Programmable Logic Device (PLD) CPLD (Complex Programmable Logic Device), UV-erasable
Technology CMOS 5 V CMOS
Number of Macrocells 192 —
Usable Gates 3,750 —
Pin-to-Pin Delay (tPD) 15 ns (fastest speed grade); 55 ns (this part) —
Counter Frequency (fCNT) up to 76.9 MHz —
Propagation Delay (tPD, this part) 55 ns —
Packhaging CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) 84-pin Ceramic Pin Grid Array (CPGA), code S-CPGA-P84
Uri ng Pagpapasok Through-Hole (PGA) Through-hole PGA socket
Erasure Method UV (windowed ceramic package) —
Volte ng Pagbibigay [DATA_NEEDED: typical VCC range] —
Maximum User I/O [DATA_NEEDED: exact I/O count for CPGA-84] —
Temperature na Operasyon [DATA_NEEDED: commercial/industrial/military grade] [DATA_NEEDED: operating temperature range]
Tindminan RoHS Non-compliant (contains lead in ceramic PGA) non_compliant (ceramic CPGA with MIL-STD-883 screening)
Process Node [DATA_NEEDED: CMOS process geometry] —
Programming Interface JTAG-compatible (per MAX 5000 family) —
Family — MAX 5000
Macrocells — 192
Propagation Delay (tPD) — 45 ns (-2 speed grade)
Maximum Internal Clock Frequency — 33.3 MHz
Supply Voltage (VCC, nominal) — 5 V
Dedicated Inputs — 7
User I/O Pins — 64
Package Outline — 28.45 mm square (approx.)
Military Screening — MIL-STD-883 (per '883' suffix)
JEDEC Package Code — S-CPGA-P84

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