EPM5192JC-1 vs EPM5192JC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-1 sa pamamagitan ng Altera at EPM5192JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC-1 EPM5192JC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 —
Device Type CPLD - Complex Programmable Logic Device —
Technology CMOS, UV-Erasable / OTP —
Macrocells 192 192
Usable Gates 3750 —
Propagation Delay (tPD) 40 ns (speed grade -1) 45 ns
Maximum Internal Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V —
User I/O Pins 84 64
Package Type 84-pin Ceramic Quad Flat Pack (CQFP), windowed —
JEDEC Package Code S-CQCC-J84 —
Temperature na Operasyon 0 C to +70 C (commercial) —
Configuration Memory UV-EPROM (erasable under UV lamp) —
Programming Interface Altera MAX programming interface (parallel, pre-JTAG for this family) —
Process CMOS EPROM —
I/O Standard TTL/CMOS 5 V compatible —
Device Family — MAX 5000
Product Type — UV-erasable Programmable Logic Device (PLD)
Logic Array Blocks (LABs) — 12
Interconnect — Programmable Interconnect Array (PIA)
Dedicated Inputs — 7
External Clock Inputs — 1
Maksimum na Taktiko ng Oras — 40 MHz
Process Technology — CMOS
Packhaging — 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed)
Uri ng Pagpapasok — Surface Mount
Number of Terminals — 84
Programming Method — UV-erase / EPROM
Hanay ng Temperature na Operasyon — [DATA_NEEDED: operating temperature range]
Tindminan RoHS — [DATA_NEEDED: RoHS compliance]

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