EPM5192JC-1N vs EPM5192JI-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-1N sa pamamagitan ng Altera at EPM5192JI-1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JC-1N | EPM5192JI-1 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD - Complex Programmable Logic Device | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Usable Gates | 3750 | — |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs (GCLK) | 1 | — |
| Propagation Delay (tPD) | 40 ns | 55 ns |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.5 V to 5.5 V (nominal 5 V) |
| Technology | CMOS EPROM (UV-erasable) | — |
| Packhaging | 84-pin Ceramic Quad Flat Pack (CQFP) | 84-pin JLCC (Windowed ceramic J-lead) |
| JEDEC Package Code | S-CQCC-J84 | — |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial temperature range] | Industrial, -40 C to +85 C |
| Programming Interface | JTAG / Altera ByteBlaster | — |
| Process Technology | — | CMOS EPROM |
| Configuration Memory | — | UV-erasable EPROM |
| Programming Method | — | External EPROM programmer (via programming hardware) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Speed Grade | — | -1 (slowest grade in EPM5192 family) |
| Logic Element per Macrocell | — | 1 D flip-flop + AND/OR array |