EPM5192JC68 vs EPM5192JC-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC68 sa pamamagitan ng Altera at EPM5192JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC68 EPM5192JC-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Device Family MAX 5000 —
Product Type EPLD (Erasable Programmable Logic Device) —
Logic Elements / Macrocells 192 macrocells —
User I/O Pins 76 84
Bilang ng Pins 68 —
Package Type PLCC-68 (J-Lead) 84-pin Ceramic Quad Flat Pack (CQFP), windowed
Temperature na Operasyon 0C to 70C (commercial, JC suffix) 0 C to +70 C (commercial)
Volte ng Pagbibigay [DATA_NEEDED: VCC] —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD] —
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX] —
Configuration Memory UV-Erasable EPROM UV-EPROM (erasable under UV lamp)
Programmable Interconnect Programmable Logic Array + Macrocells —
Dedicated Inputs 12 —
Clock Pins 4 dedicated —
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] —
Programming Tool MAX+PLUS II (legacy) —
Family — MAX 5000
Device Type — CPLD - Complex Programmable Logic Device
Technology — CMOS, UV-Erasable / OTP
Macrocells — 192
Usable Gates — 3750
Propagation Delay (tPD) — 40 ns (speed grade -1)
Maximum Internal Frequency (fMAX) — 62.5 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V
JEDEC Package Code — S-CQCC-J84
Programming Interface — Altera MAX programming interface (parallel, pre-JTAG for this family)
Process — CMOS EPROM
I/O Standard — TTL/CMOS 5 V compatible

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