EPM5192JI vs EPM5192LI-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JI sa pamamagitan ng Altera at EPM5192LI-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JI EPM5192LI-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 5000 MAX 5000
Device Type EPLD (UV-erasable CMOS Programmable Logic Device) EPLD (UV-Erasable/OTP Complex PLD)
Macrocells 192 192
Logic Array Blocks (LABs) 12 —
User I/O Pins 64 [DATA_NEEDED: user I/O count for JLCC variant]
Dedicated Inputs 7 —
Propagation Delay (tpd) 55 ns —
Volte ng Pagbibigay 4.75 V to 5.25 V (nominal 5 V) 5 V
Technology CMOS EPROM, UV-erasable —
Packhaging 84-pin PLCC (windowed, J-suffix ceramic) —
Temperature na Operasyon -40 C to +125 C (industrial, I-suffix) [DATA_NEEDED: industrial vs military range]
Uri ng Pagpapasok Surface Mount (PLCC socket recommended for UV erasure) Surface Mount (JLCC with J-leads)
Tindminan RoHS [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] [DATA_NEEDED: RoHS status of ceramic LI variant]
Programming Method Altera MAX 5000 programming algorithm (device programmer) —
Erasure Method UV exposure through windowed package —
Usable Gates — 3,750
Maximum Toggle Frequency — 40 MHz
Propagation Delay (tPD) — [DATA_NEEDED: tPD in ns at -1 grade]
Package Type — JLCC (windowed, ceramic, UV-erasable)
Process Technology — CMOS EPROM, UV-erasable
Speed Grade — -1
Bilang ng Pin — [DATA_NEEDED: pin count of LI package]
Level ng MSL — [DATA_NEEDED: MSL level]
Lead Free — [DATA_NEEDED: lead-free]
Programmable Interconnect — Programmable Interconnect Array (PIA)
Architecture — EEPROM/EPROM-based, non-volatile, instant-on

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