EPM5192JM vs EPM5192GM-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JM sa pamamagitan ng Altera at EPM5192GM-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JM EPM5192GM-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 5000 MAX 5000
Device Type UV-Erasable Programmable Logic Device (EPLD) —
Macrocells 192 —
Maximum User I/O 64 —
Dedicated Inputs 7 —
Total Input Channels 72 —
Propagation Delay (tPD) 55 ns —
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) —
Technology CMOS, UV-erasable —
Packhaging 84-pin Ceramic JLCC with quartz window (J84) CPGA-84 (Windowed Ceramic PGA)
Hanay ng Temperature na Operasyon -55 C to +125 C (military grade, 'M' suffix) [DATA_NEEDED: commercial/industrial/military grade]
Logic Architecture Shared product-term AND/OR, programmable polarity —
Programming Method UV erase + EPROM programmer, JEDEC map —
Development Tool MAX+PLUS II (legacy Altera toolchain) Altera MAX+PLUS II (legacy)
Compliance MIL-STD-883 processing available on /883B suffix variants —
Logic Cells — 192
Propagation Delay (tpd) — 55 ns
Process Technology — CMOS
Programmable Element — UV-erasable EPROM
Bilang ng Pin — 84
Volte ng Pagbibigay — [DATA_NEEDED: VCC nominal]
Programmable Macrocells — 192
User I/O Pins — [DATA_NEEDED: user I/O count]
Uri ng Pagpapasok — Through-Hole (Pin Grid Array socket)
RoHS Compliance — unknown (legacy ceramic PGA)
Lead-Free Status — unknown
Programming Interface — Altera ByteBlaster / JEDEC bitstream

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