EPM5192LC-25 vs EPM5192JC-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-25 sa pamamagitan ng Altera at EPM5192JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LC-25 EPM5192JC-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 5000 MAX 5000
Macrocells 192 192
Logic Elements 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) —
Pin-to-Pin Delay (tPD) 25 ns —
Speed Grade -25 (25 ns) —
Packhaging JLCC-84 (ceramic J-lead chip carrier) —
Uri ng Pagpapasok Surface Mount —
Programmable Technology UV-erasable / OTP (EPROM-based) —
Programming Interface JTAG / Altera programming hardware (legacy) Altera MAX programming interface (parallel, pre-JTAG for this family)
Temperature na Operasyon 0C to +70C (commercial) 0 C to +70 C (commercial)
Volte ng Pagbibigay 5 V (typical, MAX 5000) —
I/O Standard TTL-compatible TTL/CMOS 5 V compatible
Configuration Memory Non-volatile EPROM (on-chip) UV-EPROM (erasable under UV lamp)
Manufacturer Altera Corporation (now Intel PSG) —
Tindminan RoHS Unknown (legacy ceramic package typically non-RoHS) —
Device Type — CPLD - Complex Programmable Logic Device
Technology — CMOS, UV-Erasable / OTP
Usable Gates — 3750
Propagation Delay (tPD) — 40 ns (speed grade -1)
Maximum Internal Frequency (fMAX) — 62.5 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V
User I/O Pins — 84
Package Type — 84-pin Ceramic Quad Flat Pack (CQFP), windowed
JEDEC Package Code — S-CQCC-J84
Process — CMOS EPROM

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