EPM5192LC-25 vs EPM5192JC-1 比較
詳細並排比較 EPM5192LC-25 由 Altera 與 EPM5192JC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-25 | EPM5192JC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Elements | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Speed Grade | -25 (25 ns) | — |
| 封裝 | JLCC-84 (ceramic J-lead chip carrier) | — |
| 安裝類型 | Surface Mount | — |
| Programmable Technology | UV-erasable / OTP (EPROM-based) | — |
| Programming Interface | JTAG / Altera programming hardware (legacy) | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| 工作溫度 | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| 供應電壓 | 5 V (typical, MAX 5000) | — |
| I/O Standard | TTL-compatible | TTL/CMOS 5 V compatible |
| Configuration Memory | Non-volatile EPROM (on-chip) | UV-EPROM (erasable under UV lamp) |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| RoHS 狀態 | Unknown (legacy ceramic package typically non-RoHS) | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Technology | — | CMOS, UV-Erasable / OTP |
| Usable Gates | — | 3750 |
| Propagation Delay (tPD) | — | 40 ns (speed grade -1) |
| Maximum Internal Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| User I/O Pins | — | 84 |
| Package Type | — | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| JEDEC Package Code | — | S-CQCC-J84 |
| Process | — | CMOS EPROM |