EPM5192LC-2N vs EPM5192LC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-2N sa pamamagitan ng Altera at EPM5192LC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LC-2N EPM5192LC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 7000S
Macrocells 192 192
Flip-Flops 192 —
Logic Elements 192 macrocells (PAL/GAL-style AND-OR array) —
Package Type LC (ceramic J-leaded, windowed UV-erasable package family) —
Speed Grade -2 (tPD approximately 25 ns) —
Propagation Delay (typical) 25 ns —
Volte ng Pagbibigay 5 V (typical) —
Programmability UV-erasable EPROM cell —
Uri ng Pagpapasok Surface Mount (LC package) Surface Mount
Temperature na Operasyon Commercial (0C to +70C) - inferred from speed-grade -2 designation —
Tindminan RoHS Compliant (per -N lead-free suffix) [DATA_NEEDED: RoHS status]
Lead-Free Yes (per -N suffix) —
Architecture Programmable Logic Array (PLA) with global PIA —
Programming Interface Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) JTAG (ByteBlaster-compatible)
Logic Array Blocks (LABs) — 12
User I/O Pins — 64
Dedicated Inputs — 7
Global Clock Inputs — 1
Propagation Delay (tPD) — 55 ns (typical, commercial)
Maximum Clock Frequency (fMAX) — 50 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (nominal 5 V)
Process Technology — CMOS, UV-erasable/OTP EPROM configuration
Programmable Interconnect — Programmable Interconnect Array (PIA), fixed delay
Boundary-Scan Support — JTAG IEEE 1149.1
Operating Temperature (commercial) — 0C to +70C
Packhaging — JLCC-68 (windowed ceramic, LC suffix)

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