EPM5192LI vs EPM5192LC84-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LI sa pamamagitan ng Altera at EPM5192LC84-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LI | EPM5192LC84-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (UV-Erasable / OTP Complex PLD) |
| Macrocells | 192 | 192 |
| Usable Gates | 3,750 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Maximum Operating Frequency | 40 MHz | — |
| Propagation Delay (tPD) | 55 ns | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable / OTP |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| User I/O Pins | 64 | — |
| Packhaging | 84-pin PQCC (J84) | 84-pin PLCC (LC) |
| JEDEC Package Code | S-PQCC-J84 | — |
| Hanay ng Temperature na Operasyon | Industrial (-40C to +85C) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | unknown | Non-compliant (SnPb lead finish typical for this vintage) |
| Family | — | MAX 5000 |
| Speed Grade | — | -2 |
| Volte ng Pagbibigay | — | 5 V (TTL-compatible I/O) |
| Logic Elements | — | AND-OR array with macrocell flip-flops |
| Programming Method | — | Altera legacy programmer (JEDEC bitstream) |
| Temperature na Operasyon | — | Commercial (0C to +70C) |
| Katayuan ng Lifecycle | — | Obsolete (last Altera MAX 5000 production) |
| JTAG Support | — | Vendor-specific programming interface (pre-IEEE 1532) |
| I/O Standard | — | TTL, 5V CMOS-compatible |