EPM5192LI84 vs EPM5192ALI84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LI84 sa pamamagitan ng Altera at EPM5192ALI84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM5192ALI84-20 - 192-Macrocell MAX 5000 PLD, 84-Pin J-Lead | Altera
EPM5192ALI84-20 ObsoletePagsanggunian na paghahambing
| Parametro | EPM5192LI84 | EPM5192ALI84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable/OTP Complex PLD (CPLD) | — |
| Usable Gates | 3,750 gates | — |
| Macro Cells | 192 | — |
| Maximum Toggle Frequency | 40 MHz | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| User I/O Pins | 64 (max) | — |
| Hanay ng Temperature na Operasyon | -40 °C to +85 °C (industrial) | — |
| Package Type | 84-pin PLCC (J-lead, package code J84/QCCJ) | PLCC-84 (PQCC-84) |
| Uri ng Pagpapasok | Surface Mount (socket-compatible) | Surface Mount (PLCC socket compatible) |
| Configuration Memory | OTP / UV-erasable EPROM | — |
| Programming Method | Stand-alone programmer (no JTAG on LI84 OTP variant) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - Altera MAX 5000 series is generally legacy and may not be RoHS compliant] |
| Logic Compatibility | TTL-compatible I/O | — |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (UV-erasable / OTP Complex PLD) |
| Macrocells | — | 192 |
| Process Technology | — | CMOS, EPROM-based |
| Propagation Delay (tPD) | — | 20 ns (pin-compatible speed grade) |
| User I/O Pins (max) | — | 84 (in PLCC-84 package) |
| Volte ng Pagbibigay | — | 5 V (single supply, TTL-compatible I/O) |
| Operating Temperature Grade | — | Industrial (I) |
| Package Code | — | QCCJ (Plastic Leaded Chip Carrier, J-bend) |
| No. of Terminals | — | 84 |
| Form of Terminal | — | J-BEND |
| Programmability | — | UV-erasable / one-time programmable (OTP) |
| Logic Type | — | Combinatorial and registered, per-macrocell DFF |
| I/O Standard | — | TTL-compatible |