EPM5192LI84 vs EPM5192ALI84-20 比較

詳細並排比較 EPM5192LI84 由 Altera 與 EPM5192ALI84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM5192LI84 EPM5192ALI84-20
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Device Family MAX 5000 —
Product Type UV-Erasable/OTP Complex PLD (CPLD) —
Usable Gates 3,750 gates —
Macro Cells 192 —
Maximum Toggle Frequency 40 MHz —
Pin-to-Pin Delay (tPD) 25 ns —
Supply Voltage (VCC) 5 V (single supply) —
User I/O Pins 64 (max) —
工作溫度範圍 -40 °C to +85 °C (industrial) —
Package Type 84-pin PLCC (J-lead, package code J84/QCCJ) PLCC-84 (PQCC-84)
安裝類型 Surface Mount (socket-compatible) Surface Mount (PLCC socket compatible)
Configuration Memory OTP / UV-erasable EPROM —
Programming Method Stand-alone programmer (no JTAG on LI84 OTP variant) —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status - Altera MAX 5000 series is generally legacy and may not be RoHS compliant]
Logic Compatibility TTL-compatible I/O —
Family — MAX 5000
Device Type — EPLD (UV-erasable / OTP Complex PLD)
Macrocells — 192
Process Technology — CMOS, EPROM-based
Propagation Delay (tPD) — 20 ns (pin-compatible speed grade)
User I/O Pins (max) — 84 (in PLCC-84 package)
供應電壓 — 5 V (single supply, TTL-compatible I/O)
Operating Temperature Grade — Industrial (I)
Package Code — QCCJ (Plastic Leaded Chip Carrier, J-bend)
No. of Terminals — 84
Form of Terminal — J-BEND
Programmability — UV-erasable / one-time programmable (OTP)
Logic Type — Combinatorial and registered, per-macrocell DFF
I/O Standard — TTL-compatible

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