EPM570GT100C3N vs EPM570GT100I5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570GT100C3N sa pamamagitan ng Altera at EPM570GT100I5 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM570GT100C3N - MAX II CPLD 440 Macrocells 76 I/O TQFP-100 | Intel
EPM570GT100C3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM570GT100C3N | EPM570GT100I5 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | — |
| Series | MAX II G (Green) | MAX II |
| Logic Elements | 570 | — |
| Macrocells | 440 | 440 |
| User I/O Pins | 76 | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Propagation Delay (tPD max) | 5.4 ns | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V (1.8 V typical) | — |
| I/O Voltage Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Process Technology | 0.18 um | — |
| Temperature na Operasyon | 0C to 85C (TJ, commercial) | -40 C to +100 C (Industrial, "I5") |
| Packhaging | 100-pin TQFP (14x14 mm) | 100-pin TQFP (14x14 mm, 0.5 mm pitch) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (Gull-wing leads) |
| Programmable Type | In-System Programmable (Flash, non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| Tindminan RoHS | Lead free / RoHS Compliant | Compliant |
| Logic Elements (LE) | — | 570 |
| Maximum User I/O Pins | — | 76 |
| Propagation Delay (tPD) | — | 5.4 ns (typ) |
| Internal Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| User I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Programmability | — | In-System Programmable (ISP) via JTAG, non-volatile flash |
| Configuration Time | — | Instant-On (< 1 ms, no external PROM required) |
| Typical Active Current | — | [DATA_NEEDED: typical active ICC] |
| Speed Grade | — | GT (fast) |
| JTAG Support | — | IEEE 1149.1 boundary scan |
| Global Clock Networks | — | 4 |