EPM570T100C5 vs EPM570T100A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570T100C5 sa pamamagitan ng Intel at EPM570T100A5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570T100C5 | EPM570T100A5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | — |
| Family | MAX II CPLD | — |
| Logic Elements | 570 | 570 |
| Macrocells | 440 | 440 |
| Maximum User I/O Pins | 76 | — |
| Propagation Delay (tpd) | 5.4 ns (max) | — |
| Maximum Frequency | 201.1 MHz | — |
| Process Technology | 0.18 µm | — |
| Internal Supply Voltage | 2.5 V / 3.3 V | — |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory | 8 Kbits | — |
| Packhaging | TQFP-100 (14x14 mm) | 100-pin TQFP |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0°C to 85°C (TJ) | -40 °C to +125 °C (industrial) |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) - ISP |
| Tindminan RoHS | Compliant | Compliant |
| Device Family | — | MAX II |
| User I/O Pins | — | 76 |
| Number of Logic Array Blocks (LABs) | — | 57 |
| Pin-to-Pin Logic Delay (tPD) | — | 5.4 ns |
| Maximum Internal Frequency | — | 304 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V (typical) |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| User Flash Memory (UFM) | — | 8 Kbits |
| Configuration Memory | — | On-chip non-volatile flash |