EPM570T144C3 vs EPM570T144C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570T144C3 sa pamamagitan ng Intel at EPM570T144C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570T144C3 | EPM570T144C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | MAX II |
| Device | EPM570 | — |
| Logic Elements (LEs) | 440 | 570 |
| Macro Cells | 440 | — |
| Maximum User I/O Pins | 160 | 116 |
| User Flash Memory | 4.0 Kbits | — |
| Logic Array Blocks (LABs) | 8 | — |
| Speed Grade | C3 (5.4 ns tPD1) | — |
| Process Technology | 0.18 µm | 0.18 µm 6-layer-metal flash |
| Core Voltage (VCCINT) | 3.3 V (internal regulator generates 2.5 V core) | 1.8 V (typical, internally regulated) |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank) |
| Maximum Frequency (internal) | 304 MHz | — |
| Propagation Delay (tPD1) | 5.4 ns | — |
| Packhaging | 144-pin TQFP (20 mm × 20 mm × 1.4 mm) | TQFP-144 (20 × 20 mm, 0.5 mm pitch) |
| Operating Temperature (Commercial) | 0 °C to +85 °C | — |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | IEEE 1149.1 JTAG (in-system programmable) |
| Configuration | Non-volatile, instant-on (single-chip) | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Compliant |
| Series | — | MAX II Device |
| Macrocells | — | 440 |
| User I/Os | — | 116 |
| Internal User Flash Memory | — | 8 Kbit |
| Global Clocks | — | 4 |
| Propagation Delay (tPD) | — | 5.5 ns (typical, [DATA_NEEDED: exact speed grade]) |
| Maximum Frequency (fMAX) | — | 201.1 MHz |
| Temperature na Operasyon | — | 0 °C to +85 °C (commercial, C5 grade) |
| Uri ng Pagpapasok | — | Surface Mount |
| Configuration Storage | — | On-chip non-volatile flash |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO) |
| Lead-Free | — | Yes |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Design Software | — | Intel Quartus II (MAX II device support) |