EPM570T144I5N vs EPM570T144I5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570T144I5N sa pamamagitan ng Intel at EPM570T144I5 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570T144I5N | EPM570T144I5 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Family | MAX II | MAX II |
| Logic Elements | 570 LE | — |
| Macrocells | 440 | — |
| Maximum Pin-to-Pin Delay (tPD1) | 8.7 ns | — |
| Maximum Frequency (fCNT) | 304 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Supply Voltage - Core (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Temperature na Operasyon | -40C to +100C (industrial) | -40 °C to +100 °C (industrial) |
| Speed Grade | I5N | — |
| Process Technology | 0.18 um CMOS, 6-layer-metal flash | 0.18 µm flash |
| Packhaging | TQFP-144 (22 mm x 22 mm, 0.5 mm pitch) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) |
| Boundary-Scan Test | IEEE 1149.1 compliant | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells (Logic Elements) | — | 440 |
| User I/O | — | 116 |
| Pin-to-Pin Delay (tPD1) | — | 5.4 ns |
| Maximum Frequency (fMAX) | — | 304 MHz |
| Supply Voltage - Core | — | 1.8 V |
| Supply Voltage - I/O Banks | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Packhaging / Kaso | — | TQFP-144 (144-LQFP, 20 x 20 mm) |