EPM7128AEFC100-5 vs EPM7128BTC100-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128AEFC100-5 sa pamamagitan ng Altera at EPM7128BTC100-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128AEFC100-5 - MAX 7000A CPLD, 128MC, 5ns, 100-FBGA | Altera
EPM7128AEFC100-5 ✓ NakahandaIntel
EPM7128BTC100-10 - MAX 7000B CPLD, 128 Macrocells, 10ns | Intel
EPM7128BTC100-10 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM7128AEFC100-5 | EPM7128BTC100-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 7000A | MAX 7000B |
| Logic Family / Base Number | EPM7128A | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2.5K |
| Propagation Delay (tPD) | 5 ns | — |
| Internal Frequency (fMAX) | 192.3 MHz | — |
| User I/Os | 84 | 84 |
| Logic Family | CMOS | — |
| Volte ng Pagbibigay | 3.3 V | — |
| Packhaging | 100-ball FBGA (FineLine BGA) | TQFP-100 |
| Bilang ng Pin | 100 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programmable Type | EEPROM (In-System Programmable) | — |
| Temperature na Operasyon | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| JTAG Support | Yes (IEEE 1149.1 Boundary Scan) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant (lead-free) |
| Logic Array Blocks (LABs) | — | 8 (16 macrocells each) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | 125 MHz |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 3.3 V (5V tolerant inputs) |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Technology | — | CMOS EEPROM |