EPM7128ATC100-10 vs EPM7128STI100-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128ATC100-10 sa pamamagitan ng Altera at EPM7128STI100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7128ATC100-10 EPM7128STI100-10N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 7000A MAX 7000S
Architecture Multiple Array MatriX (MAX) CMOS EEPROM-based CPLD
Macrocells 128 128
Logic Array Blocks (LABs) 4 8
Usable Gates 2.5K 2,500 (up to 5,000 family max)
User I/O Pins 68 —
Pin-to-Pin Logic Delay 4.5 ns —
Counter Frequency (max) 227.3 MHz —
Speed Grade -10 (10 ns) —
Core Supply Voltage 3.3 V —
I/O Logic Level Support 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Program Memory EEPROM (non-volatile) —
In-System Programmability Yes (IEEE 1149.1 JTAG) Yes (JTAG IEEE 1149.1)
Packhaging 100-pin TQFP (TC100) 100-pin TQFP
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon 0C to +70C (commercial) -40C to +85C (Industrial)
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Maximum User I/O — 84
Pin-to-Pin Logic Delay (tPD) — 10 ns
Maximum Counter Frequency — 175.4 MHz
Supply Voltage (VCC) — 5 V
JTAG Boundary-Scan — Yes (BST)
Level ng MSL — [DATA_NEEDED: MSL level]
Open-Drain I/O Option — Available (per MAX 7000A feature set)

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