EPM7128SLC84-10 vs EPM7128ELC84-12 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SLC84-10 sa pamamagitan ng Intel at EPM7128ELC84-12 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7128SLC84-10 | EPM7128ELC84-12 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000 (MAX 7000E series) |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | 128 |
| Logic Gates | 2500 | — |
| User I/Os | 68 | 84 |
| Total Package Pins | 84 | — |
| Packhaging | PLCC-84 (J-lead) | 84-pin PLCC (J-Lead, QCCJ) |
| Propagation Delay (tpd) | 10 ns | — |
| Maximum Operating Frequency | 125 MHz | — |
| Internal Frequency | 250 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5 V | — |
| Program Memory Type | EEPROM (in-system programmable) | — |
| JTAG (IEEE 1149.1) | Yes | — |
| Temperature na Operasyon | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Surface Mount (J-bend) | Surface Mount (PLCC socket compatible) |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Non-compliant (contains lead in PLCC) | Non-compliant (legacy 5V part, SnPb finish) |
| Logic Family | — | CMOS, EEPROM-based |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tpd1) | — | 12 ns |
| Internal Global Clock Frequency | — | 90.9 MHz |
| Setup Time | — | 4.5 ns |
| Supply Voltage (VCCINT / VCCIO) | — | 5 V (4.75 V to 5.25 V) |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Bilang ng Pin | — | 84 |