EPM7128SLI84-10 vs EPM7128SLI84-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SLI84-10 sa pamamagitan ng Altera at EPM7128SLI84-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndPagsanggunian na paghahambing
| Parametro | EPM7128SLI84-10 | EPM7128SLI84-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2.5K | 2,500 |
| Macro Cells | 128 | — |
| User I/Os | 68 | 68 |
| Logic Array Blocks (LABs) | 8 | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Internal Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | 4.75 V to 5.25 V (5 V typical) |
| Configuration Memory | EEPROM (in-system programmable) | — |
| Temperature na Operasyon | -40 °C to +85 °C (industrial) | -40 C to +85 C (Industrial) |
| Packhaging | 84-pin PLCC | 84-pin PLCC (J-Lead) |
| Uri ng Pagpapasok | Surface Mount / Socket | Surface Mount |
| Process Technology | CMOS | CMOS EEPROM |
| JTAG Support | Yes (IEEE 1149.1) | — |
| Tindminan RoHS | [DATA_NEEDED: lead-free variant is -10N suffix] | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] |
| Logic Cells / Macro Cells | — | 128 macro cells |
| Number of Logic Elements / Blocks | — | 16 Logic Array Blocks (LABs) |
| Maximum Frequency (fMAX) | — | 125 MHz |
| I/O Voltage Tolerance | — | 3.3 V / 5 V MultiVolt I/O |
| Programmability | — | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std 1149.1 compliant |
| Lead-Free | — | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] |