EPM7128SQC100-7N vs EPM7128STC100-6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SQC100-7N sa pamamagitan ng Intel at EPM7128STC100-6N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N ObsoleteAltera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128SQC100-7N | EPM7128STC100-6N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Program Memory Type | EEPROM | — |
| Number of Macrocells | 128 | — |
| Number of Logic Array Blocks | 8 | — |
| Number of Global Clocks | 2 | — |
| Product Terms per Macrocell | 32 | — |
| Usable Gates | 2,500 | 2,500 |
| System Gates | 5,000 (max) | — |
| Maximum User I/Os | 84 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Counter Speed | 175.4 MHz | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Operating Voltage (Core) | 5.0 V | — |
| I/O Standard Support | multiVolt (2.5V, 3.3V, 5.0V) | — |
| Packhaging | 100-pin PQFP (QFP-100) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Tindminan RoHS | Compliant (lead-free 'N' suffix) | Non-Compliant (lead-bearing package) |
| Process Technology | 0.30 µm CMOS EEPROM | CMOS EEPROM |
| Security Bit | Programmable (one per device) | — |
| Macro Cells | — | 128 |
| User I/Os | — | 84 |
| Logic Family | — | CMOS |
| Bilang ng Pins | — | 100 |
| Package Type | — | TQFP-100 |
| Maximum Internal Frequency | — | 147.1 MHz |
| Internal Counter Frequency | — | 250 MHz |
| Propagation Delay (tPD) | — | 6 ns |
| Pin-to-Pin Delay | — | 4.5 ns |
| Supply Voltage (VCCIO) | — | 5 V |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| Uri ng Pagpapasok | — | Surface Mount |