EPM7128SQI100-15N vs EPM7128SQC100-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SQI100-15N sa pamamagitan ng Intel at EPM7128SQC100-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM7128SQC100-15 EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM7128SQI100-15N EPM7128SQC100-15
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Huling Pagbili
Presyo ng Yunit (USD) — $8.20
Family MAX 7000S MAX 7000
Device Type EE-PLD / CPLD CPLD (Complex Programmable Logic Device)
Macrocells 128 128
User I/Os 80 84
Usable Gates 2,500 (typical) —
Propagation Delay (tPD) 15 ns —
Maximum Frequency (fCNT) 76.9 MHz —
Core Supply Voltage (VCCINT) 4.5 V to 5.5 V —
I/O Logic Levels 3.3 V or 5 V (multi-volt I/O) —
Operating Temperature Grade Industrial (-40C to +85C) —
Packhaging PQFP-100 (R-PQFP-G100) 100-pin PQFP (Plastic Quad Flat Pack)
Terminal Form Gull Wing —
Package Code QFP —
Uri ng Pagpapasok Surface Mount Surface Mount
Process Technology CMOS —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Non-volatile Configuration EEPROM (instant-on) —
Tindminan RoHS Lead-free (N suffix) Non-compliant (SnPb lead finish - legacy PQFP)
Logic Array Blocks (LABs) — 4 (16 macrocells each)
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Frequency (fMAX) — [DATA_NEEDED: fMAX value]
Typical Gate Count — 2,500 gates
Supply Voltage (VCCINT) — 5 V (5% tolerance)
Programming Technology — EEPROM (in-system programmable via JTAG)
JTAG Interface — IEEE Std. 1149.1 compliant
Temperature na Operasyon — 0C to +70C (Commercial)
Level ng MSL — 3 (168 hours)

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