EPM7128STC100-10N vs EPM7128STC100-6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128STC100-10N sa pamamagitan ng Altera at EPM7128STC100-6N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndAltera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128STC100-10N | EPM7128STC100-6N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Product Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | — |
| User I/Os | 84 | 84 |
| Propagation Delay (tPD) | 10 ns | 6 ns |
| Internal Frequency (fMAX) | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (MultiVolt) | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Packhaging | 100-pin TQFP (14 x 14 x 1 mm) | — |
| Temperature na Operasyon | 0 C to +70 C (commercial) | 0C to +70C (Commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant (Pb-free "N" suffix) | Non-Compliant (lead-bearing package) |
| Lead-Free | Yes | — |
| Macro Cells | — | 128 |
| Logic Family | — | CMOS |
| Bilang ng Pins | — | 100 |
| Package Type | — | TQFP-100 |
| Maximum Internal Frequency | — | 147.1 MHz |
| Internal Counter Frequency | — | 250 MHz |
| Pin-to-Pin Delay | — | 4.5 ns |
| Supply Voltage (VCCIO) | — | 5 V |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |