EPM7128STC100-15N vs EPM7128STC100-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128STC100-15N sa pamamagitan ng Intel at EPM7128STC100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7128STC100-15N EPM7128STC100-10N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Product Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Family MAX 7000S MAX 7000S
Usable Gates 2,500 2,500
Macro Cells 128 —
Logic Array Blocks (LABs) 8 (16 macro cells each) 8 (16 macrocells each)
Maximum User I/O 84 —
Pin-to-Pin Logic Delay (tPD) 15 ns (-15 speed grade) —
Maximum Internal Frequency 76.9 MHz —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Supply Voltage (VCCIO) 3.3 V or 5 V (per bank) —
Technology CMOS EEPROM, in-system programmable —
Packhaging 100-pin TQFP 100-pin TQFP (14 x 14 x 1 mm)
Temperature na Operasyon 0C to +70C (commercial) 0 C to +70 C (commercial)
JTAG (IEEE 1149.1) Yes - in-system programming —
Output Options Totem-pole or open-drain (per pin) —
Dedicated Inputs 4 global inputs —
Tindminan RoHS Non-RoHS (legacy SnPb finish typical) Compliant (Pb-free "N" suffix)
Katayuan ng Lifecycle Obsolete (PDN effective 2017-06-01) —
Macrocells — 128
User I/Os — 84
Propagation Delay (tPD) — 10 ns
Internal Frequency (fMAX) — 100 MHz
Supply Voltage (VCCINT) — 5 V
I/O Voltage (VCCIO) — 3.3 V or 5 V (MultiVolt)
Process Technology — CMOS EEPROM
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Uri ng Pagpapasok — Surface Mount
Lead-Free — Yes

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