EPM7128STC100-6 vs EPM7128STC100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128STC100-6 sa pamamagitan ng Intel at EPM7128STC100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7128STC100-6 EPM7128STC100-10
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 7000S MAX 7000S
Macrocells 128 —
Equivalent Gates 2,500 —
User I/O Pins 84 —
Pin-to-Pin Delay (tPD) 6 ns —
Maximum Internal Frequency (fCNT) 147.1 MHz —
Supply Voltage (VCCINT / VCCIO) 5 V —
Packhaging 100-pin TQFP (STC100) TQFP-100 (C100)
Uri ng Pagpapasok Surface Mount Surface Mount
Programming Interface JTAG (IEEE Std. 1149.1) / ISP —
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C (commercial)
PCI Compliance 33 MHz PCI Local Bus Rev. 2.2 (-6/-7/-10 grades) —
Lead Pitch 1.0 mm (TQFP) —
Lead-Free / RoHS Contains lead (non-RoHS original; -6N variant is lead-free) —
Configuration Memory On-chip EEPROM (non-volatile) —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 128
Usable Gates — 2,500
User I/Os — 84
Logic Array Blocks — 8 (16 macrocells per LAB)
Propagation Delay (tPD) — 10 ns
Internal Counter Frequency (fCNT) — 100 MHz
Logic Family — CMOS
Supply Voltage (VCCINT) — 5 V
MultiVolt I/O Voltage — 3.3 V / 5 V
Bilang ng Pin — 100
Programmability — In-System Programmable (JTAG, IEEE 1149.1), EEPROM
Tindminan RoHS — [DATA_NEEDED: RoHS compliance status not in provided data]

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