EPM7192EGI160-20 vs EPM7192EQC160-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7192EGI160-20 sa pamamagitan ng Intel at EPM7192EQC160-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 ObsoletePagsanggunian na paghahambing
| Parametro | EPM7192EGI160-20 | EPM7192EQC160-20 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 7000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | — |
| Logic Array Blocks | 4 | — |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 4 | — |
| Pin-to-Pin Delay (tpd) | 20 ns | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | 4.75 V to 5.25 V |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (JTAG IEEE Std. 1149.1) | — |
| Packhaging | 160-pin CPGA (Ceramic Pin Grid Array) | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status - non-RoHS era part] |
| Programming Interface | JTAG (ByteBlaster / USB-Blaster compatible) | — |
| Series | — | MAX 7000 |
| Programmable Type | — | EE PLD (EEPROM-based) |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of User I/O Pins | — | 124 (per package), 36 (per data source variant description) |
| Delay Time (tPD) | — | 20 ns |
| Internal Counter Frequency (fCNT) | — | 100 MHz typical |
| Temperature na Operasyon | — | -40C to +85C (industrial) |
| Packhaging / Kaso | — | 160-BQFP / 160-PQFP (28x28 mm) |
| Uri ng Pagpapasok | — | Surface Mount |
| In-System Programmable (ISP) | — | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) |
| Programmable Security Bit | — | Yes |
| Power-Saving Mode | — | Yes, programmable per macrocell |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |