EPM7192SQC160-15 vs EPM7192SQC160-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7192SQC160-15 sa pamamagitan ng Altera at EPM7192SQC160-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7192SQC160-10N - 192-Macrocell MAX 7000S CPLD, 10ns, 160-Pin PQFP | Altera
EPM7192SQC160-10N NrndPagsanggunian na paghahambing
| Parametro | EPM7192SQC160-15 | EPM7192SQC160-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | MAX 7000S | MAX 7000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 192 | — |
| Number of Logic Array Blocks | 4 | — |
| Number of Usable Gates | 3750 | — |
| User I/O Pins | 124 | 124 |
| Pin-to-Pin Logic Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 76.9 MHz | 100 MHz |
| Volte ng Pagbibigay | 5.0 V | — |
| Programmability | In-System (ISP) via JTAG IEEE Std 1149.1 | — |
| Configuration Memory | EEPROM, non-volatile | — |
| Packhaging | PQFP-160 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Process Technology | CMOS, EEPROM-based | 0.30 µm CMOS EEPROM |
| Series | — | MAX 7000S |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Usable Gates | — | 3,750 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Packhaging / Kaso | — | 160-BQFP (PQFP, 0.65 mm pitch) |
| Temperature na Operasyon | — | [DATA_NEEDED: commercial/industrial grade] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance status] |