EPM7256AEQC208-5N vs EPM7256AEQI208-7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256AEQC208-5N sa pamamagitan ng Altera at EPM7256AEQI208-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7256AEQC208-5N | EPM7256AEQI208-7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 7000A | MAX 7000A |
| Logic Family / Base Technology | CMOS, EEPROM-based | — |
| Usable Gates | 5,000 | 5,000 |
| Macrocells | 256 | 256 |
| User I/Os | 164 | — |
| Dedicated Inputs | 16 | — |
| Bilang ng Pins | 208 | — |
| Packhaging | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin PQFP (FQFP) |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Maximum Internal Frequency | 172.4 MHz | 126.6 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 5.5 ns | 7.5 ns |
| Speed Grade | -5 | -7 |
| Temperature na Operasyon | 0 C to +70 C (Commercial) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | unknown | Compliant (N suffix) |
| Level ng MSL | [DATA_NEEDED: MSL Level] | — |
| User I/O Pins | — | 164 |
| Logic Array Blocks | — | 16 |
| Volte ng Pagbibigay | — | 3.3 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| Number of Terminals | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Shape | — | Square |
| Operating Temperature Grade | — | Industrial |
| Lead Finish | — | [DATA_NEEDED: lead finish] |