EPM7256AEQI208-7N vs EPM7256AEQC208-5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256AEQI208-7N sa pamamagitan ng Altera at EPM7256AEQC208-5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7256AEQI208-7N | EPM7256AEQC208-5N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 7000A | MAX 7000A |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5,000 |
| User I/O Pins | 164 | — |
| Logic Array Blocks | 16 | — |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns | 5.5 ns |
| Maximum Internal Frequency | 126.6 MHz | 172.4 MHz |
| Volte ng Pagbibigay | 3.3 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| Packhaging | 208-pin PQFP (FQFP) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Number of Terminals | 208 | — |
| Terminal Form | Gull Wing | — |
| Package Shape | Square | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Operating Temperature Grade | Industrial | — |
| Speed Grade | -7 | -5 |
| Tindminan RoHS | Compliant (N suffix) | unknown |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Logic Family / Base Technology | — | CMOS, EEPROM-based |
| User I/Os | — | 164 |
| Dedicated Inputs | — | 16 |
| Bilang ng Pins | — | 208 |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Temperature na Operasyon | — | 0 C to +70 C (Commercial) |
| Programming Interface | — | JTAG (IEEE Std. 1149.1) / ISP |
| Level ng MSL | — | [DATA_NEEDED: MSL Level] |