EPM7256ATI144-10 vs EPM7256AQC208-7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256ATI144-10 sa pamamagitan ng Altera at EPM7256AQC208-7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7256ATI144-10 | EPM7256AQC208-7 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 7000A | MAX 7000A |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Usable Gates | 5,000 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | 93.5 MHz | — |
| User I/O Pins | 100 | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 2.5 V or 3.3 V | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Packhaging | 144-pin TQFP | 208-Pin PQFP (28 x 28 mm) |
| Hanay ng Temperature na Operasyon | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Non-compliant (legacy Altera marking) | [DATA_NEEDED: RoHS status] |
| Process Technology | EEPROM-based CMOS | — |
| Programmable Type | — | In System Programmable (ISP), EEPROM-based |
| Usable Gates | — | 5,000 |
| Maximum User I/O Pins | — | 164 |
| Pin-to-Pin Logic Delay (tPD) | — | 7 ns |
| Maximum Counter Frequency | — | 125 MHz |
| Internal Toggle Frequency | — | 227.3 MHz |
| Supply Voltage - Internal | — | 3.0 V to 3.6 V |
| I/O Voltage Compatibility | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Supplier Device Package | — | 208-PQFP (28x28) |
| JTAG Interface | — | IEEE 1149.1 (JTAG) boundary scan |
| Configuration Memory | — | EEPROM (non-volatile) |
| Speed Grade | — | -7 |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |