EPM7256SQC208-15 vs EPM7256AQC208-7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256SQC208-15 sa pamamagitan ng Altera at EPM7256AQC208-7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7256SQC208-15 EPM7256AQC208-7
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family MAX 7000S MAX 7000A
Series EPM7256 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 256 256
Logic Array Blocks (LABs) 16 16
Usable Gates 5000 5,000
User I/O Pins 164 —
Pin-to-Pin Delay (tPD) 15 ns —
Supply Voltage (VCCINT) 4.75 V to 5.25 V —
Hanay ng Temperature na Operasyon 0 C to +70 C (Commercial) 0C to +70C (commercial)
Packhaging 208-pin PQFP (28x28 mm) 208-Pin PQFP (28 x 28 mm)
Uri ng Pagpapasok Surface Mount Surface Mount
Programmable Power Mode Yes (per-macrocell turbo-bit) —
JTAG (IEEE 1149.1) Boundary-Scan Yes —
In-System Programmability (ISP) Yes —
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
Tindminan RoHS Contains lead / RoHS non-compliant (per third-party listing) [DATA_NEEDED: RoHS status]
Lead-Free Status Contains lead —
Programmable Type — In System Programmable (ISP), EEPROM-based
Maximum User I/O Pins — 164
Pin-to-Pin Logic Delay (tPD) — 7 ns
Maximum Counter Frequency — 125 MHz
Internal Toggle Frequency — 227.3 MHz
Supply Voltage - Internal — 3.0 V to 3.6 V
I/O Voltage Compatibility — 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O)
Supplier Device Package — 208-PQFP (28x28)
JTAG Interface — IEEE 1149.1 (JTAG) boundary scan
Speed Grade — -7
Level ng MSL — [DATA_NEEDED: MSL level]

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