EPM7256SQC208-15 vs EPM7256AQC208-7 比較
詳細並排比較 EPM7256SQC208-15 由 Altera 與 EPM7256AQC208-7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7256SQC208-15 | EPM7256AQC208-7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | MAX 7000S | MAX 7000A |
| Series | EPM7256 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 5000 | 5,000 |
| User I/O Pins | 164 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| 工作溫度範圍 | 0 C to +70 C (Commercial) | 0C to +70C (commercial) |
| 封裝 | 208-pin PQFP (28x28 mm) | 208-Pin PQFP (28 x 28 mm) |
| 安裝類型 | Surface Mount | Surface Mount |
| Programmable Power Mode | Yes (per-macrocell turbo-bit) | — |
| JTAG (IEEE 1149.1) Boundary-Scan | Yes | — |
| In-System Programmability (ISP) | Yes | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| RoHS 狀態 | Contains lead / RoHS non-compliant (per third-party listing) | [DATA_NEEDED: RoHS status] |
| Lead-Free Status | Contains lead | — |
| Programmable Type | — | In System Programmable (ISP), EEPROM-based |
| Maximum User I/O Pins | — | 164 |
| Pin-to-Pin Logic Delay (tPD) | — | 7 ns |
| Maximum Counter Frequency | — | 125 MHz |
| Internal Toggle Frequency | — | 227.3 MHz |
| Supply Voltage - Internal | — | 3.0 V to 3.6 V |
| I/O Voltage Compatibility | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Supplier Device Package | — | 208-PQFP (28x28) |
| JTAG Interface | — | IEEE 1149.1 (JTAG) boundary scan |
| Speed Grade | — | -7 |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |