EPM7256SRC208-10 vs EPM7256SRC208-15N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256SRC208-10 sa pamamagitan ng Intel at EPM7256SRC208-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM7256SRC208-15N EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera

EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera

EPM7256SRC208-15N Obsolete

Pagsanggunian na paghahambing

Parametro EPM7256SRC208-10 EPM7256SRC208-15N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 7000S —
Device Type CPLD (Complex Programmable Logic Device) —
Number of Macrocells 256 —
Number of Logic Array Blocks (LABs) 16 —
Number of Gates 5000 —
Number of User I/O Pins 164 —
Maximum Propagation Delay (tPD) 10 ns —
Maximum Operating Frequency 100 MHz —
Supply Voltage (Internal) 4.75 V to 5.25 V —
Programmable Type In System Programmable (ISP, JTAG) —
Configuration Technology EEPROM —
Packhaging 208-pin RQFP (BFQFP) exposed pad, 28x28 mm 208-pin RQFP (PowerQuad Flat Pack)
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon 0C to +70C (TA, commercial) 0C to +70C (commercial)
Terminal Form Gull Wing —
Package Shape Square —
Product Status Obsolete —
Tindminan RoHS [DATA_NEEDED: RoHS status] Compliant (N suffix)
Series — MAX 7000S
Macrocells — 256
Usable Gates — 5,000
User I/O Pins — 164
Logic Array Blocks (LABs) — 16
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Counter Frequency — 76.9 MHz
Volte ng Pagbibigay — 5 V
Configuration Memory — EEPROM (non-volatile)
In-System Programmability — Yes (IEEE 1149.1 JTAG)
I/O Standard — 5 V TTL/CMOS compatible
Lead Free — Yes (N suffix)
Level ng MSL — [DATA_NEEDED: MSL level]
Number of Terminals — 208

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