EPM9320ALC84-15 vs EPM9320LC84-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALC84-15 sa pamamagitan ng Altera at EPM9320LC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320ALC84-15 EPM9320LC84-20
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 9000 CPLD MAX 9000
Macrocells 320 320
Usable Gates 6000 —
Propagation Delay (tPD) 16 ns 16 ns
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
User I/O 56 —
Logic Array Blocks (LABs) 16 —
Technology CMOS, EEPROM-based configuration —
Packhaging 84-pin PLCC (S-PQCC-J84, J-lead) PLCC-84 (Plastic Leaded Chip Carrier)
Uri ng Pagpapasok Through-hole / socket —
Programming Interface JTAG (IEEE 1149.1) / ISP —
Temperature na Operasyon -40C to +85C (industrial) 0 C to 70 C
Tindminan RoHS [DATA_NEEDED: rohs status] [DATA_NEEDED: RoHS status]
Level ng Sensitivity sa Asid ng Moisture (MSL) MSL-3 (168 hours per fpgalink.com) —
Lead-Free / Halogen-Free [DATA_NEEDED: lead free status] —
RoHS3 Compliance ROHS3 Compliant (per fpgalink.com listing) —
Device Type — CPLD - Complex Programmable Logic Device
User I/Os — 60
Logic Family — CMOS (EEPROM-based)
Pins — 84
Internal Counter Frequency — 118 MHz
Volte ng Pagbibigay — 5.0 V
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Dedicated Inputs — 4 (global clock / clear / OE)
Architecture — Multiple Array MatriX (MAX), 3rd generation
PCI Compliance — PCI Local Bus Specification Rev. 2.2

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