EPM9320ALC84-20 vs EPM9320ALI84-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALC84-20 sa pamamagitan ng Altera at EPM9320ALI84-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320ALC84-20 | EPM9320ALI84-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | 20 |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Packhaging | PLCC-84 | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Process Technology | 0.5 µm CMOS EEPROM | CMOS EEPROM |
| Volte ng Pagbibigay | 5.0 V | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Temperature na Operasyon | [DATA_NEEDED: commercial or industrial grade] | -40C to +85C (industrial) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Configuration Memory | Non-volatile EEPROM | EEPROM, non-volatile |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| Tindminan RoHS | [DATA_NEEDED: per Altera datasheet] | — |
| Architecture | — | MAX (Multiple Array MatriX), 3rd generation |
| Usable Gates | — | 6,000 to 12,000 |
| User I/O Pins | — | 56 |
| Pin-to-Pin Delay | — | 10 ns |
| Maximum Counter Frequency | — | 144.9 MHz |
| VCCINT (Core Supply) | — | 5.0 V |
| VCCIO (I/O Supply) | — | 3.3 V or 5.0 V |
| Input Logic Levels | — | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |