EPM9320ALI84-10N vs EPM9320ALC84-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALI84-10N sa pamamagitan ng Altera at EPM9320ALC84-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320ALI84-10N | EPM9320ALC84-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | MAX (Multiple Array MatriX) with FastTrack Interconnect |
| Process Technology | CMOS EEPROM | — |
| Usable Gates | 6,000 to 12,000 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | 16 |
| User I/O Pins | 56 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Maximum Counter Frequency | 144.9 MHz | — |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | 5.0 V ISP via IEEE 1149.1 JTAG |
| Packhaging | 84-pin PLCC (J-lead, 1.270 mm pitch) | 84-pin PLCC (J-Lead) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount / Through-Hole (PLCC socket) |
| Temperature na Operasyon | -40C to +85C (industrial) | [DATA_NEEDED: commercial/industrial grade] |
| Configuration Memory | EEPROM, non-volatile | — |
| Device | — | EPM9320 |
| Maximum User I/O Pins | — | 52 |
| Dedicated Inputs | — | 16 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Technology | — | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Tindminan RoHS | — | [DATA_NEEDED] |
| Non-Volatile Configuration | — | Yes (EEPROM cell, powers up in known state) |