EPM9320ALI84-10N vs EPM9320ALC84-10 比較
詳細な並列比較: EPM9320ALI84-10N メーカー: Altera および EPM9320ALC84-10 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9320ALI84-10N | EPM9320ALC84-10 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.95 | $19.80 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | MAX (Multiple Array MatriX) with FastTrack Interconnect |
| Process Technology | CMOS EEPROM | — |
| Usable Gates | 6,000 to 12,000 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | 16 |
| User I/O Pins | 56 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Maximum Counter Frequency | 144.9 MHz | — |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | 5.0 V ISP via IEEE 1149.1 JTAG |
| パッケージ | 84-pin PLCC (J-lead, 1.270 mm pitch) | 84-pin PLCC (J-Lead) |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Surface Mount / Through-Hole (PLCC socket) |
| 動作温度 | -40C to +85C (industrial) | [DATA_NEEDED: commercial/industrial grade] |
| Configuration Memory | EEPROM, non-volatile | — |
| Device | — | EPM9320 |
| Maximum User I/O Pins | — | 52 |
| Dedicated Inputs | — | 16 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Technology | — | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| RoHS ステータス | — | [DATA_NEEDED] |
| Non-Volatile Configuration | — | Yes (EEPROM cell, powers up in known state) |