EPM9320ALI84-10N vs EPM9320ALC84-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALI84-10N sa pamamagitan ng Altera at EPM9320ALC84-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320ALI84-10N EPM9320ALC84-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 9000 MAX 9000 CPLD
Device Type CPLD (Complex Programmable Logic Device) —
Architecture MAX (Multiple Array MatriX), 3rd generation —
Process Technology CMOS EEPROM —
Usable Gates 6,000 to 12,000 6000
Macrocells 320 320
Logic Array Blocks (LABs) 20 16
User I/O Pins 56 —
Pin-to-Pin Delay 10 ns —
Maximum Counter Frequency 144.9 MHz —
VCCINT (Core Supply) 5.0 V —
VCCIO (I/O Supply) 3.3 V or 5.0 V —
Input Logic Levels TTL-compatible (at 5.0 V VCCINT) —
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) —
Packhaging 84-pin PLCC (J-lead, 1.270 mm pitch) 84-pin PLCC (S-PQCC-J84, J-lead)
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Through-hole / socket
Temperature na Operasyon -40C to +85C (industrial) -40C to +85C (industrial)
Configuration Memory EEPROM, non-volatile —
Propagation Delay (tPD) — 16 ns
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
User I/O — 56
Technology — CMOS, EEPROM-based configuration
Programming Interface — JTAG (IEEE 1149.1) / ISP
Tindminan RoHS — [DATA_NEEDED: rohs status]
Level ng Sensitivity sa Asid ng Moisture (MSL) — MSL-3 (168 hours per fpgalink.com)
Lead-Free / Halogen-Free — [DATA_NEEDED: lead free status]
RoHS3 Compliance — ROHS3 Compliant (per fpgalink.com listing)

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