EPM9320ALI84-10N vs EPM9320ALC84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALI84-10N sa pamamagitan ng Altera at EPM9320ALC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320ALI84-10N | EPM9320ALC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | — |
| Process Technology | CMOS EEPROM | 0.5 µm CMOS EEPROM |
| Usable Gates | 6,000 to 12,000 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | 16 |
| User I/O Pins | 56 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Maximum Counter Frequency | 144.9 MHz | — |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | — |
| Packhaging | 84-pin PLCC (J-lead, 1.270 mm pitch) | PLCC-84 |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Temperature na Operasyon | -40C to +85C (industrial) | [DATA_NEEDED: commercial or industrial grade] |
| Configuration Memory | EEPROM, non-volatile | Non-volatile EEPROM |
| Maximum User I/Os | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Volte ng Pagbibigay | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Design Software | — | MAX+PLUS II / Quartus II (legacy) |
| Tindminan RoHS | — | [DATA_NEEDED: per Altera datasheet] |