EPM9320ARC208-10 vs EPM9320ALC84-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ARC208-10 sa pamamagitan ng Altera at EPM9320ALC84-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM9320ARC208-10 EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM9320ARC208-10 EPM9320ALC84-10
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Device Family MAX 9000 —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 320 320
Usable Gates 6,000 —
Pin-to-Pin Delay (tPD) 10 ns 10 ns
Maximum Frequency 144.9 MHz —
Volte ng Pagbibigay 5.0 V —
Logic Blocks (LABs) 16 —
Programmability EEPROM, in-system programmable via JTAG —
JTAG Support IEEE Std. 1149.1 compliant —
Speed/Power Optimization Per-macrocell programmable, 50% power mode available —
Packhaging RQFP-208 (Power Quad Flat Pack) 84-pin PLCC (J-Lead)
Uri ng Pagpapasok Surface Mount Surface Mount / Through-Hole (PLCC socket)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] [DATA_NEEDED: commercial/industrial grade]
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED]
Family — MAX 9000
Device — EPM9320
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 52
Dedicated Inputs — 16
Speed Grade — -10 (10 ns pin-to-pin delay)
Supply Voltage (VCCINT) — 5.0 V
In-System Programmability — 5.0 V ISP via IEEE 1149.1 JTAG
Technology — CMOS EEPROM-based, third-generation MAX
PCI Compliance — PCI Local Bus Specification Rev. 2.2 (speed grade -10)
Non-Volatile Configuration — Yes (EEPROM cell, powers up in known state)
Architecture — MAX (Multiple Array MatriX) with FastTrack Interconnect

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