EPM9320ARC208-10N vs EPM9320RC208-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ARC208-10N sa pamamagitan ng Altera at EPM9320RC208-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320ARC208-10N | EPM9320RC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 320 | — |
| Logic Gates | 6,000 gates | — |
| Logic Array Blocks (LABs) | 16 | [DATA_NEEDED: LAB count] |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| User I/O Pins | 168 | — |
| Dedicated Input Pins | 12 | — |
| Packhaging | 208-pin RQFP (BFQFP with exposed pad) | 208-pin RQFP (RC) |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | 0C to +70C (Commercial) | Commercial (0C to +70C) - 'C' suffix |
| Programming Interface | IEEE Std. 1149.1 JTAG | JTAG (ByteBlaster/BitBlaster) |
| Configuration Memory | Non-volatile EEPROM | — |
| Tindminan RoHS | Compliant (lead-free 'N' suffix) | ROHS3 Compliant (per fpgalink listing) |
| Usable Gates | — | 6,000 |
| Macrocells | — | 320 |
| Volte ng Pagbibigay | — | 5 V |
| Speed Grade | — | -10 |
| Non-volatile Configuration | — | Yes (EPROM/EEPROM based) |
| Design Tool Support | — | MAX+PLUS II, Quartus (legacy) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |